Integrated Circuits (IC) frequently require an on-chip ramp or clock generator. It is desirable for the clock or ramp signal to be independent of process variations, supply voltage and temperature.
Many ICs use a relaxation oscillator for generation of a ramp or clock. Usually the timing elements used by this circuit are a resistor and capacitor. Each of these components varies by +/−20%, to at least some extent due to process corner. This results in the on-chip clock varying by +/−28%. To reduce the spread in clock variation with process corner it is desirable to compensate for process variations.
The use of trimming to reduce variation in the frequency of a clock may add to the cost of ICs that require an on-chip ramp or clock generator.
U.S. Pat. No. 6,091,286 (Philips Electronics North America Corporation, Jul. 18, 2000) describes an integrated reference circuit having controlled temperature dependence. Specifically, the patent describes that mobility in an FET is used as a time standard to develop a reference component which may be fully integrated and which is temperature stable to an arbitrary desired accuracy. The large temperature dependence of mobility is compensated by applying a gate bias voltage having a predetermined variation in value with respect to temperature. In one embodiment the bias voltage of the FET is given a temperature dependence which results in the drain current of the FET being substantially constant with respect to temperature. This current is then used to charge or discharge a capacitor, yielding an R-C product which may be implemented in integrated form. A plurality of PTAT current sources are combined, and FET threshold bias compensation is provided by a bias source that is separate from the temperature dependent current sources.
U.S. Pat. No. 4,843,265 (Dallas Semiconductor Corporation, Jun. 27, 1989) describes that a temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) connected to the terminals of a charged capacitor. A bias voltage connected to the gate of the FET varies with temperature in a manner to compensate for the changes in current which flows from the capacitor through the FET due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.
The negative temperature co-efficient in the bias voltage is provided by three summed BJT base-emitter voltages in combination with a scaled and temperature invariant bandgap voltage. Hence, it cannot be arbitrarily scaled. Furthermore, the FET threshold compensation is provided by a second FET that does not have its source at the same potential as that of the first FET. Hence, threshold voltage cancellation is not perfect. Furthermore, a timing capacitor is connected across the drain-source terminals of the FET.
U.S. Pat. No. 6,157,270 (Exar Corporation, Dec. 5, 2000) relates to a programmable oscillator, and describes that an oscillator circuit generates an output frequency that is substantially independent of power supply and temperature variations. The oscillator circuit can be implemented using conventional complementary metal-oxide-semiconductor technology. A FET is used in linear mode.
U.S. Pat. No. 6,496,056 (Agere Systems Inc, Dec. 17, 2002) relates to process tolerant integrated chip design. It describes that an operating parameter of an integrated circuit is made substantially insensitive to process variations by configuring the circuit such that an environmental parameter, e.g., supply voltage to a portion of the circuit, is made a function of one or more process parameters, e.g., conduction threshold voltages and mobilities in that portion of the circuit. In an arrangement, the circuit operating parameter is an oscillation period of a ring oscillator. A voltage regulator generates a reference voltage which is determined at least in part based on known process parameter variations in the ring oscillator. The ring oscillator utilizes the reference voltage generated by the voltage regulator as its supply voltage.
US patent application 2006/0226922 A1 (Texas Instruments Inc, published Oct. 12, 2006) relates to a process, supply, and temperature insensitive integrated time reference circuit. Specifically, it describes that a relaxation oscillator includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. A charging current is proportional to 1/R.
U.S. Pat. No. 5,070,311 (SGS-Thomson Microelectronics SA, Dec. 3, 1991) relates to an integrated circuit with adjustable oscillator with frequency independent of the supply voltage. Specifically, it describes that, to enable the making, in an integrated circuit, of an internal clock, the frequency of which is adjustable and does not depend on the general supply voltage Vcc of the circuit, a relaxation oscillator is used. The relaxation oscillator is built in the following way: weighted individual current sources may be selectively connected in parallel under the control of a register containing frequency adjusting data. These sources charge and discharge a capacitor. A threshold comparator determines a high threshold Vh and a low threshold Vb to trigger respectively the discharging and the charging of the capacitor. The difference Vh-Vb is made proportional to the currents of the elementary sources. A discrete charging capacitor is used.
Paper “A 7-MHz process, temperature and supply compensated clock oscillator in 0.25 μm CMOS” (Sundaresan, K.; Brouse, K. C.; U-Yen, K.; Ayazi, F.; Allen, P. E., ISCAS 03: Proceedings of the 2003 International Symposium on Circuits and Systems, 2003; Volume 1, May 25-28, 2003, Page(s): I-693-I-696) relates to the design and characterization of a process, temperature and supply compensation technique for a clock generator based on a three-stage differential ring oscillator. The variation of the frequency of the oscillator with temperature and process is discussed and an adaptive biasing scheme incorporating a unique combination of a process corner sensing scheme and a temperature compensating network is considered. Specifically, the paper describes that a biasing circuit changes the control voltage of the differential ring oscillator to maintain a constant frequency. The technique includes a process corner sensing scheme.
In the field of signal generation, it is desirable to provide cost-effective generation of a clock or ramp signal that is independent of process variations, supply voltage and temperature. Moreover, there is a need to provide apparatuses and methods for improved signal generation, and apparatuses and methods for improved trimming of the temperature coefficient of a signal.